CMOS image sensors are increasingly being used as low cost imaging devices. A CMOS image sensor circuit includes a focal plane array of pixel cells, each one of the cells includes a photogate, photoconductor, or photodiode having an associated charge accumulation region within a substrate for accumulating photo-generated charge. Each pixel cell may include a transistor for transferring charge from the charge accumulation region to a sensing node and a transistor for resetting the sensing node to a predetermined charge level prior to charge transference. The pixel cell may also include a source follower transistor for receiving and amplifying charge from the sensing node and an access transistor for controlling the readout of the cell contents from the source follower transistor.
In a CMOS image sensor, the active elements of a pixel cell perform the necessary functions of: (1) photon to charge conversion; (2) accumulation of image charge; (3) transfer of charge to the sensing node accompanied by charge amplification; (4) resetting the sensing node to a known state; (5) selection of a pixel for readout; and (6) output and amplification of a signal representing pixel charge from the sensing node.
CMOS image sensors of the type discussed above are generally known as discussed, for example, in Nixon et al., “256×256 CMOS Active Pixel Sensor Camera-on-a-Chip,” IEEE Journal of Solid-State Circuits, Vol. 31(12), pp. 2046-2050 (1996); and Mendis et al., “CMOS Active Pixel Image Sensors,” IEEE Transactions on Electron Devices, Vol. 41(3), pp. 452-453 (1994). See also U.S. Pat. Nos. 6,177,333 and 6,204,524, which describe the operation of conventional CMOS image sensors and are assigned to Micron Technology, Inc., the contents of which are incorporated herein by reference.
A schematic diagram of a conventional four transistor (4T) CMOS pixel cell 10 is shown in FIG. 1. The CMOS pixel cell 10 generally comprises a photo-conversion device 23 for generating and collecting charge generated by light incident on the pixel cell 10, and a transfer transistor 17 for transferring photoelectric charges from the photo-conversion device 23 to a sensing node, typically a floating diffusion region 5. The floating diffusion region 5 is electrically connected to the gate of an output source follower transistor 19. The pixel cell 10 also includes a reset transistor 16 for resetting the floating diffusion region 5 to a predetermined voltage Vaa-pix; and a row select transistor 18 for outputting a signal from the source follower transistor 19 to an output terminal in response to an address signal.
FIG. 2 is a cross-sectional view of a portion of the pixel cell 10 of FIG. 1 showing the photo-conversion device 23, transfer transistor 17 and reset transistor 16. The exemplary photo-conversion device 23 may be formed as a pinned photodiode as shown. The photodiode has a p-n-p construction comprising a p-type surface layer 22 and an n-type photodiode region 21 within a p-type substrate 11. The photodiode photo-conversion device 23 is adjacent to and partially underneath the transfer transistor 17. The reset transistor 16 is on a side of the transfer transistor 17 opposite the photo-conversion device 23. As shown in FIG. 2, the reset transistor 16 includes a source/drain region 2. The floating diffusion region 5 is located between the transfer and reset transistors 17, 16.
In the CMOS pixel cell 10 depicted in FIGS. 1 and 2, electrons are generated by light incident on the photo-conversion device 23 and are stored in the n-type photodiode region 21. These charges are transferred to the floating diffusion region 5 by the transfer transistor 17 when the transfer transistor 17 is activated. The source follower transistor 19 produces an output signal based on the transferred charges applied to its gate. A maximum output signal is proportional to the number of electrons extracted from the n-type photodiode region 21.
A shallow trench isolation (STI) region 3 can be formed adjacent to an active element, such as the n-type charge accumulation region 21, and it is used to isolate the pixel cell 10 from other pixel cells and devices of the image sensor. The STI region 3 is typically formed using a conventional STI process. The STI region 3 is typically lined with an oxide liner 38 and filled with a dielectric material 37. Also, the STI region 3 can include a nitride liner 39. The nitride liner 39 provides several benefits, including improved corner rounding near the STI region 3 corners, reduced stress adjacent the STI region 3, and reduced leakage.
During conventional STI-forming processes, a trench is formed to a depth D1 between about 1000 Angstroms (Å) and about 6000 Å. The sidewalls 9 of the trench are formed at an angle θ1, which is typically between 80 degrees and 90 degrees.
A common problem associated with the above described STI region 3 is dangling bonds (e.g., dangling silicon (Si—) bonds 231 (FIG. 4A)) at the surface of the substrate 11 and along the trench bottom 8 and sidewalls 9. The dangling bonds 231 (FIG. 4A) create an uneven surface and may also cause a high density of trap sites along the trench bottom 8 and sidewalls 9. As a result of these trap sites formed along the bottom 8 and sidewalls 9 of the STI region 3, current generation near and along the trench bottom 8 and sidewalls 9 can be significant. Current generated from trap sites inside or near the photo-conversion device's 23 depletion region causes undesired dark current and increased fixed pattern noise.
Further, as the size of pixel cells continues to decrease, due to desired scaling, the impact of the uneven silicon surface of the STI sidewalls becomes more pronounced and dark current generated from the STI regions increases. Effective isolation in scaled pixel cells is increasingly important as pixels cells are being made smaller, but this isolation needs to be done without decreasing the quantum efficiency of the pixel cell or increasing the dark current near the STI region.
Similarly, high quality isolation techniques are also important in fabricating memory and other integrated circuit devices. STI is a conventional technique used, for example, in isolating conventional memory cells, such as dynamic random access memory (DRAM) cells, portions of which are shown in FIG. 3. Referring to FIG. 3, deeper STI regions 117 have been found to provide better isolation between portions of memory cells 112 such as between capacitors 114 and active regions 119 in a substrate 101; however, there is a limit to how deep the STI region 117 can be made in the substrate 101. If the STI region 117 is too deep, filling the STI trench with oxide layers 115 will result in voids 111 or cracks in the trench. Thus, there is a desire and need to isolate active areas of memory devices without relying on a deep or heavily doped trench region.
Accordingly, it is desirable to have an improved isolation structure for reducing dark current while maintaining high quantum efficiency for imager pixel cells. Simple methods of forming the improved isolation structure are also needed. In addition, there is needed an effective isolation technique which can also be used in high density integrated circuit applications, including within DRAM memory devices.